As semiconductor fabrication technology continues to progress, devices such as field effect transistors (FET) continue to get smaller and less expensive. The design and layout for such devices are constrained by technology specific minimum sizes, spacings, alignments and overlaps of the various structures of the device and the fabrication means. During manufacturing a percentage of the devices are defective due to process variations.
A typical power MOSFET device may have thousands or millions of parallel MOSFET cells. The large number of parallel linked cells enable the device to handle high current and have a low on resistance. Generally, the higher the current carrying capability of the device, the high the number of cells there are in the device. When a single cell in the device is defective, such as a gate-to-source or source-to-drain short, the defect typically damages the entire device. Therefore, when one cell is defective, the whole device has to be discarded, reducing the manufacturing yield. The massive parallel cell structure also makes it difficult to screen the devices. In particular, non-catastrophic defects between source-to-gate and drain-to-gate are not easily detectable. The non-catastrophic device may therefore cause reliability issued with the device and/or the electronics in which it is utilized.